This project focused on the design and implementation of a 24GHz All-Digital Phase-Locked Loop (ADPLL), a critical component in high-frequency RF systems such as software-defined radios (SDRs), millimeter-wave communication systems, and radar applications. The ADPLL replaces traditional analog phase-locked loops, offering enhanced programmability, process scalability, and improved integration with digital systems.
A key challenge in ADPLL design is achieving low phase noise and high-frequency stability while maintaining a fully digital architecture. This project explored Digital Controlled Oscillators (DCOs), Time-to-Digital Converters (TDCs), and high-speed frequency synthesis techniques to achieve optimal performance.
As the Lead Designer & Researcher, I was responsible for:
• Architecting the ADPLL system and defining key design specifications
• Designing a Digital Controlled Oscillator (DCO) optimized for low phase noise
• Developing Time-to-Digital Converters (TDCs) for precise phase detection
• Simulating and validating system performance using RF and circuit modeling tools
• Optimizing phase noise, frequency synthesis, and tuning stability
• Electronic Design Automation (EDA) Engineer - I was responsible for setting up and configuring all EDA tools
• Literature Review: Investigated phase noise reduction techniques in ADPLLs
• Noise Modeling & Analysis: Studied the impact of TDC noise, divider noise, and DCO phase noise
• Electromagnetic (EM) Simulations: Modeled high-frequency resonator structures for DCO optimization
• Comparison with Traditional PLLs: Benchmarked ADPLL performance against analog PLL architectures
• RF & Circuit Simulation: Cadence Virtuoso, Agilent ADS
• Electromagnetic Analysis: Sonnet EM
• Modeling & Automation: MATLAB, Perl scripting, Verilog-A for automated circuit generation
• Fabrication & Testing: FreePDK45nm for CMOS integration
This project focused on the design and implementation of a 24GHz All-Digital Phase-Locked Loop (ADPLL), a critical component in high-frequency RF systems such as software-defined radios (SDRs), millimeter-wave communication systems, and radar applications. The ADPLL replaces traditional analog phase-locked loops, offering enhanced programmability, process scalability, and improved integration with digital systems.
A key challenge in ADPLL design is achieving low phase noise and high-frequency stability while maintaining a fully digital architecture. This project explored Digital Controlled Oscillators (DCOs), Time-to-Digital Converters (TDCs), and high-speed frequency synthesis techniques to achieve optimal performance.
As the Lead Designer & Researcher, I was responsible for:
• Architecting the ADPLL system and defining key design specifications
• Designing a Digital Controlled Oscillator (DCO) optimized for low phase noise
• Developing Time-to-Digital Converters (TDCs) for precise phase detection
• Simulating and validating system performance using RF and circuit modeling tools
• Optimizing phase noise, frequency synthesis, and tuning stability
• Electronic Design Automation (EDA) Engineer - I was responsible for setting up and configuring all EDA tools
• RF & Circuit Simulation: Cadence Virtuoso, Agilent ADS
• Electromagnetic Analysis: Sonnet EM
• Modeling & Automation: MATLAB, Perl scripting, Verilog-A for automated circuit generation
• Fabrication & Testing: FreePDK45nm for CMOS integration
• Literature Review: Investigated phase noise reduction techniques in ADPLLs
• Noise Modeling & Analysis: Studied the impact of TDC noise, divider noise, and DCO phase noise
• Electromagnetic (EM) Simulations: Modeled high-frequency resonator structures for DCO optimization
• Comparison with Traditional PLLs: Benchmarked ADPLL performance against analog PLL architectures
This project focused on the design and implementation of a 24GHz All-Digital Phase-Locked Loop (ADPLL), a critical component in high-frequency RF systems such as software-defined radios (SDRs), millimeter-wave communication systems, and radar applications. The ADPLL replaces traditional analog phase-locked loops, offering enhanced programmability, process scalability, and improved integration with digital systems.
A key challenge in ADPLL design is achieving low phase noise and high-frequency stability while maintaining a fully digital architecture. This project explored Digital Controlled Oscillators (DCOs), Time-to-Digital Converters (TDCs), and high-speed frequency synthesis techniques to achieve optimal performance.
As the Lead Designer & Researcher, I was responsible for:
• Architecting the ADPLL system and defining key design specifications
• Designing a Digital Controlled Oscillator (DCO) optimized for low phase noise
• Developing Time-to-Digital Converters (TDCs) for precise phase detection
• Simulating and validating system performance using RF and circuit modeling tools
• Optimizing phase noise, frequency synthesis, and tuning stability
• Electronic Design Automation (EDA) Engineer - I was responsible for setting up and configuring all EDA tools
• RF & Circuit Simulation: Cadence Virtuoso, Agilent ADS
• Electromagnetic Analysis: Sonnet EM
• Modeling & Automation: MATLAB, Perl scripting, Verilog-A for automated circuit generation
• Fabrication & Testing: FreePDK45nm for CMOS integration
• Literature Review: Investigated phase noise reduction techniques in ADPLLs
• Noise Modeling & Analysis: Studied the impact of TDC noise, divider noise, and DCO phase noise
• Electromagnetic (EM) Simulations: Modeled high-frequency resonator structures for DCO optimization
• Comparison with Traditional PLLs: Benchmarked ADPLL performance against analog PLL architectures
Objectives:
• Design a 24GHz ADPLL with digital phase and frequency control
• Develop a Digital Controlled Oscillator (DCO) with fine-tuning resolution
• Minimize phase noise and jitter for high-frequency applications
• Optimize ADPLL components for scalability in deep-submicron CMOS
Constraints:
• TDC resolution limitations—Reducing quantization noise for accurate phase detection
• DCO tuning range—Achieving fine-grain control without excessive complexity
• CMOS process constraints—Ensuring the ADPLL is manufacturable in sub-45nm nodes
• Power & area trade-offs—Balancing low-power consumption and compact layout
Key Players:
• University Research Faculty – Academic support and validation of design
• Semiconductor & RF Engineers – Feedback on real-world implementation challenges
• Industry Applications – Potential use in wireless communication and radar systems
Challenges:
• Traditional PLLs rely on analog loop filters and voltage-controlled oscillators (VCOs), which suffer from process variability and integration challenges.
• Digital PLLs (ADPLLs) eliminate analog components, but require precise digital control mechanisms for accurate frequency synthesis.
• Maintaining low phase noise in a fully digital architecture is a major challenge at 24GHz and beyond.
The Impact:
• ADPLLs enable direct digital control, reducing design complexity and improving scalability.
• Fine-tuned DCO design improves frequency accuracy, enabling better performance in SDRs and radar applications.
• Optimized TDC design reduces phase noise, improving system stability in high-frequency applications.
Step 1: System-Level ADPLL Architecture
• Defined ADPLL building blocks, including TDC, DCO, loop filter, and feedback divider.
• Investigated noise sources and their impact on overall phase noise performance.
Step 2: Digital Controlled Oscillator (DCO) Design
• Developed a 24GHz DCO using Digital Controlled Artificial Dielectric (DiCAD) structures.
• Simulated tuning characteristics and frequency stability in Sonnet EM and Cadence Virtuoso.
Step 3: Time-to-Digital Converter (TDC) Optimization
• Designed a high-resolution TDC to improve phase detection accuracy.
• Implemented quantization noise shaping techniques to enhance timing resolution.
Step 4: Simulation, Validation & Optimization
• Performed full ADPLL simulations to evaluate phase noise, jitter, and frequency locking.
• Optimized power consumption and layout area for integration in a 45nm CMOS process.
• Designed a 24GHz ADPLL architecture with digital phase control
• Developed a high-performance DCO using artificial dielectric tuning
• Implemented a precise TDC for accurate time-domain phase measurement
• Optimized phase noise performance using advanced noise-shaping techniques
• Designed a sigma-modulator to push DCO noise outside the bandwith of the oscillator.
• For residual in band noise I used a correlator to cancel accumulated residual noise
Key Success Metrics:
• Achieved fine-tuning resolution with DiCAD-based DCO
• Reduced phase noise for improved frequency stability
• Validated ADPLL performance in high-frequency RF applications
• Demonstrated manufacturability in sub-45nm CMOS technology
Long-Term Impact:
• Enhanced ADPLL performance for next-gen SDR and radar systems
• Increased digital integration for scalable semiconductor design
• Reduced dependency on analog components, improving process portability
• ADPLL technology is critical for the future of digital RF systems.
• Digital tuning techniques like DiCAD enable precise frequency control.
• Optimizing noise sources is crucial for high-performance PLL design.
• ADPLLs offer better scalability compared to traditional analog PLLs.
• Digital oscillators reduce power and improve integration in RF applications.
• This research contributes to the evolution of high-frequency digital frequency synthesis.
• The extensive modeling skills developed in this project made me a perfect fit for an entry level position at Broadcom helping produce AMI models.
• I still use these skills today as I transfer modeled calibration algorithms in System Verilog into embedded firmware.
.svg)
