I am an Embedded Systems Firmware Engineer & Software Developer in the SerDes IP Development Team at Broadcom.
My role is unique in that it blends embedded software development with deep electrical engineering expertise, spanning analog circuit design, digital communications, and DSP systems.
The IP we develop is mission-critical—powering the revenue streams of three divisions in Broadcom and establishing them as market leaders. We design high-performance SerDes IP for PCIe, Ethernet, and InfiniBand standards, enabling cutting-edge AI/ML infrastructure for the major hyper scalers. My contributions extend across 56G, 112G, and 224G SerDes, with next-gen 400G technology in progress.
My firmware is deployed across millions of devices, optimizing high-speed data transmission while ensuring industry-leading reach and low-power consumption. This directly reduces Total Cost of Ownership (TCO) for AI/ML platforms, reinforcing Broadcom’s leadership in the space.
I lead the design and implementation of adaptive algorithms and firmware-accelerated silicon debug tools, ensuring our SerDes IP meets the industry’s strictest performance and reliability standards.
Adaptive Algorithms for Performance Optimization
• I develop and maintain firmware-based calibration algorithms that compensate for analog circuit mismatches and non-linearities, ensuring optimal system performance.
• My algorithms are integral to meeting high-speed signaling requirements, allowing our SerDes designs to operate at peak performance across varying conditions.
Firmware-Driven Silicon Debug & Characterization
• Our SerDes IP goes beyond basic data transmission—I develop microcode-accelerated debug tools that enable real-time waveform capture, eye diagrams, and ISI analysis.
• These tools are critical for data collection, performance tuning, and silicon validation, directly supporting internal teams and external customers.
Leadership & Cross-Functional Collaboration
• As a technical leader and go-to expert, I oversee the end-to-end development lifecycle—from conceptualization to silicon bring-up, including debug and optimization of the final product.
• I take an ownership mindset, ensuring any issue that reaches me is resolved—whether in my domain or outside, I collaborate across teams to understand system-wide side effects and tradeoffs, ensuring delivery of both balanced and optimized solutions.
• This cross-functional approach allows me to break down silos, gain system-level expertise, and continuously increase my impact within the team.
• Languages: C/C++, Python, Verilog / SystemVerilog
• EDA & Debug Tools: Synopsys Verdi, SimVision
• Development Environment: Linux, Git, Jenkins
• Project & Collaboration Tools: JIRA, Confluence
My work at Broadcom directly contributes to industry-leading SerDes performance, improved debugging capabilities, and optimized high-speed data transmission, driving innovation in AI/ML infrastructure and high-performance computing.
Enhanced Performance & Power Efficiency:
My firmware-based adaptive algorithms optimize SerDes signal integrity, improving system-level performance while reducing power consumption across millions of deployed devices.
Accelerated Debug & Time-to-Market:
By developing firmware-accelerated silicon debug tools, I have significantly reduced silicon validation and debugging time, enabling faster product rollouts and customer support.
By adopting Object-Oriented software design practices, my code is easily ported to next generation of SerDes, enabling shorter time-to-market.
You see, not only is Broadcom the market leader in their space, but every generation we reduce our development cycle times.
Business & Market Leadership
My contributions support Broadcom’s leadership in PCIe, Ethernet, and InfiniBand SerDes, directly impacting three major revenue-generating divisions: ASICs Product Group, Core Switching Group and Physical Layer Products Group.
Cross-Team Collaboration & System-Level Impact:
I work closely with system architects, applications engineers, and hardware teams to streamline debugging, optimize performance, and ensure seamless silicon bring-up.
Next-Gen Readiness:
My work has been instrumental in developing 112G and 224G SerDes, laying the foundation for upcoming 400G SerDes technology, ensuring Broadcom remains ahead in the AI/ML networking space.
I am an Embedded Systems Firmware Engineer & Software Developer in the SerDes IP Development Team at Broadcom.
My role is unique in that it blends embedded software development with deep electrical engineering expertise, spanning analog circuit design, digital communications, and DSP systems.
The IP we develop is mission-critical—powering the revenue streams of three divisions in Broadcom and establishing them as market leaders. We design high-performance SerDes IP for PCIe, Ethernet, and InfiniBand standards, enabling cutting-edge AI/ML infrastructure for the major hyper scalers. My contributions extend across 56G, 112G, and 224G SerDes, with next-gen 400G technology in progress.
My firmware is deployed across millions of devices, optimizing high-speed data transmission while ensuring industry-leading reach and low-power consumption. This directly reduces Total Cost of Ownership (TCO) for AI/ML platforms, reinforcing Broadcom’s leadership in the space.
I lead the design and implementation of adaptive algorithms and firmware-accelerated silicon debug tools, ensuring our SerDes IP meets the industry’s strictest performance and reliability standards.
Adaptive Algorithms for Performance Optimization
• I develop and maintain firmware-based calibration algorithms that compensate for analog circuit mismatches and non-linearities, ensuring optimal system performance.
• My algorithms are integral to meeting high-speed signaling requirements, allowing our SerDes designs to operate at peak performance across varying conditions.
Firmware-Driven Silicon Debug & Characterization
• Our SerDes IP goes beyond basic data transmission—I develop microcode-accelerated debug tools that enable real-time waveform capture, eye diagrams, and ISI analysis.
• These tools are critical for data collection, performance tuning, and silicon validation, directly supporting internal teams and external customers.
Leadership & Cross-Functional Collaboration
• As a technical leader and go-to expert, I oversee the end-to-end development lifecycle—from conceptualization to silicon bring-up, including debug and optimization of the final product.
• I take an ownership mindset, ensuring any issue that reaches me is resolved—whether in my domain or outside, I collaborate across teams to understand system-wide side effects and tradeoffs, ensuring delivery of both balanced and optimized solutions.
• This cross-functional approach allows me to break down silos, gain system-level expertise, and continuously increase my impact within the team.
My work at Broadcom directly contributes to industry-leading SerDes performance, improved debugging capabilities, and optimized high-speed data transmission, driving innovation in AI/ML infrastructure and high-performance computing.
Enhanced Performance & Power Efficiency:
My firmware-based adaptive algorithms optimize SerDes signal integrity, improving system-level performance while reducing power consumption across millions of deployed devices.
Accelerated Debug & Time-to-Market:
By developing firmware-accelerated silicon debug tools, I have significantly reduced silicon validation and debugging time, enabling faster product rollouts and customer support.
By adopting Object-Oriented software design practices, my code is easily ported to next generation of SerDes, enabling shorter time-to-market.
You see, not only is Broadcom the market leader in their space, but every generation we reduce our development cycle times.
Business & Market Leadership
My contributions support Broadcom’s leadership in PCIe, Ethernet, and InfiniBand SerDes, directly impacting three major revenue-generating divisions: ASICs Product Group, Core Switching Group and Physical Layer Products Group.
Cross-Team Collaboration & System-Level Impact:
I work closely with system architects, applications engineers, and hardware teams to streamline debugging, optimize performance, and ensure seamless silicon bring-up.
Next-Gen Readiness:
My work has been instrumental in developing 112G and 224G SerDes, laying the foundation for upcoming 400G SerDes technology, ensuring Broadcom remains ahead in the AI/ML networking space.
• Languages: C/C++, Python, Verilog / SystemVerilog
• EDA & Debug Tools: Synopsys Verdi, SimVision
• Development Environment: Linux, Git, Jenkins
• Project & Collaboration Tools: JIRA, Confluence
I am an Embedded Systems Firmware Engineer & Software Developer in the SerDes IP Development Team at Broadcom.
My role is unique in that it blends embedded software development with deep electrical engineering expertise, spanning analog circuit design, digital communications, and DSP systems.
The IP we develop is mission-critical—powering the revenue streams of three divisions in Broadcom and establishing them as market leaders. We design high-performance SerDes IP for PCIe, Ethernet, and InfiniBand standards, enabling cutting-edge AI/ML infrastructure for the major hyper scalers. My contributions extend across 56G, 112G, and 224G SerDes, with next-gen 400G technology in progress.
My firmware is deployed across millions of devices, optimizing high-speed data transmission while ensuring industry-leading reach and low-power consumption. This directly reduces Total Cost of Ownership (TCO) for AI/ML platforms, reinforcing Broadcom’s leadership in the space.
I lead the design and implementation of adaptive algorithms and firmware-accelerated silicon debug tools, ensuring our SerDes IP meets the industry’s strictest performance and reliability standards.
Adaptive Algorithms for Performance Optimization
• I develop and maintain firmware-based calibration algorithms that compensate for analog circuit mismatches and non-linearities, ensuring optimal system performance.
• My algorithms are integral to meeting high-speed signaling requirements, allowing our SerDes designs to operate at peak performance across varying conditions.
Firmware-Driven Silicon Debug & Characterization
• Our SerDes IP goes beyond basic data transmission—I develop microcode-accelerated debug tools that enable real-time waveform capture, eye diagrams, and ISI analysis.
• These tools are critical for data collection, performance tuning, and silicon validation, directly supporting internal teams and external customers.
Leadership & Cross-Functional Collaboration
• As a technical leader and go-to expert, I oversee the end-to-end development lifecycle—from conceptualization to silicon bring-up, including debug and optimization of the final product.
• I take an ownership mindset, ensuring any issue that reaches me is resolved—whether in my domain or outside, I collaborate across teams to understand system-wide side effects and tradeoffs, ensuring delivery of both balanced and optimized solutions.
• This cross-functional approach allows me to break down silos, gain system-level expertise, and continuously increase my impact within the team.
My work at Broadcom directly contributes to industry-leading SerDes performance, improved debugging capabilities, and optimized high-speed data transmission, driving innovation in AI/ML infrastructure and high-performance computing.
Enhanced Performance & Power Efficiency:
My firmware-based adaptive algorithms optimize SerDes signal integrity, improving system-level performance while reducing power consumption across millions of deployed devices.
Accelerated Debug & Time-to-Market:
By developing firmware-accelerated silicon debug tools, I have significantly reduced silicon validation and debugging time, enabling faster product rollouts and customer support.
By adopting Object-Oriented software design practices, my code is easily ported to next generation of SerDes, enabling shorter time-to-market.
You see, not only is Broadcom the market leader in their space, but every generation we reduce our development cycle times.
Business & Market Leadership
My contributions support Broadcom’s leadership in PCIe, Ethernet, and InfiniBand SerDes, directly impacting three major revenue-generating divisions: ASICs Product Group, Core Switching Group and Physical Layer Products Group.
Cross-Team Collaboration & System-Level Impact:
I work closely with system architects, applications engineers, and hardware teams to streamline debugging, optimize performance, and ensure seamless silicon bring-up.
Next-Gen Readiness:
My work has been instrumental in developing 112G and 224G SerDes, laying the foundation for upcoming 400G SerDes technology, ensuring Broadcom remains ahead in the AI/ML networking space.
• Languages: C/C++, Python, Verilog / SystemVerilog
• EDA & Debug Tools: Synopsys Verdi, SimVision
• Development Environment: Linux, Git, Jenkins
• Project & Collaboration Tools: JIRA, Confluence
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